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LTM4603HV
APPLICATIO S I FOR ATIO
R PGM =
V OUT 1 . 18 V
The typical LTM4603HV application circuit is shown in
Figure 20. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 2 for speci?c external capacitor
requirements for a particular application.
V IN to V OUT Step-Down Ratios
There are restrictions in the maximum V IN and V OUT step
down ratio that can be achieved for a given input voltage.
These constraints are shown in the Typical Performance
Characteristics curves labeled V IN to V OUT Step-Down
where %V OUT is the percentage of V OUT you want to margin,
and V OUT(MARGIN) is the margin quantity in volts:
? ? 10 k
0 . 6 V V OUT ( MARGIN )
where R PGM is the resistor value to place on the MPGM
pin to ground.
The output margining will be ± margining of the value.
This is controlled by the MARG0 and MARG1 pins. See
the truth table below:
Ratio. Note that additional thermal derating may apply. See
the Thermal Considerations and Output Current Derating
section of this data sheet.
Output Voltage Programming and Margining
MARG0
LOW
LOW
HIGH
HIGH
MARG1
LOW
HIGH
LOW
HIGH
MODE
NO MARGIN
MARGIN UP
MARGIN DOWN
NO MARGIN
The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 1M and a 60.4k 0.5%
internal feedback resistor connects V OUT and V FB pins
together. The V OUT_LCL pin is connected between the 1M
and the 60.4k resistor. The 1M resistor is used to protect
against an output overvoltage condition if the V OUT_LCL
pin is not connected to the output, or if the remote sense
ampli?er output is not connected to V OUT_LCL . The output
voltage will default to 0.6V. Adding a resistor R SET from
the V FB pin to SGND pin programs the output voltage:
Input Capacitors
LTM4603HV module should be connected to a low AC
impedance DC source. Input capacitors are required to
be placed adjacent to the module. In Figure 20, the 10μF
ceramic input capacitors are selected for their ability to
handle the large RMS current into the converter. An input
bulk capacitor of 100μF is optional. This 100μF capacitor is
only needed if the input source impedance is compromised
by long inductive leads or traces.
V OUT = 0 . 6 V
60.4k + R SET
R SET
For a buck converter, the switching duty-cycle can be
estimated as:
R SET
(k Ω )
V OUT
0.6 1.2 1.5 1.8 2
D =
Table 1 . Standard 1% Resistor Values
Open 60.4 40.2 30.1 25.5
(V)
19.1
2.5
13.3
3.3
8.25
5
V OUT
V IN
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
The MPGM pin programs a current that when multiplied
by an internal 10k resistor sets up the 0.6V reference ±
I CIN ( RMS ) =
I OUT(MAX )
η %
? D ? ( 1 – D )
offset for margining. A 1.18V reference divided by the
R PGM resistor on the MPGM pin programs the current.
Calculate V OUT(MARGIN) :
In the above equation, η % is the estimated ef?ciency of
the power module. C IN can be a switcher-rated electrolytic
aluminum capacitor, OS-CON capacitor or high volume
V OUT ( MARGIN ) =
% V OUT
100
? V OUT
ceramic capacitor. Note the capacitor ripple current rat-
ings are often based on temperature and hours of life. This
makes it advisable to properly derate the input capacitor,
4603hvf
10
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